Flash EEPROMs (flash electrically erasable and programmable read only memories) are nonvolatile memories in which bit lines are divided and formed into a hierarchical structure. In this type of memory, a common row decoder is used to select word lines corresponding to the divided bit lines (sub-bit lines) so as to implement a highly concentrated word line makeup wherein memory contents may be erased in increments off blocks. One such flash EEPROM is disclosed illustratively in Japanese Published Unexamined Patent Application No. Hei 4-208566.